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1. 发明申请

US20110241205A1 SEMICONDUCTOR WITH THROUGH-SUBSTRATE INTERCONNECT 有权
标题翻译：具有通孔基板互连的半导体
公开(公告)号：US20110241205A1
公开(公告)日：2011-10-06
申请号：US13160363
申请日：2011-06-14
申请人： Kyle Kirby , Kunal Parekh
发明人： Kyle Kirby , Kunal Parekh
IPC分类号： H01L23/488 , H01L21/283 , H01L21/76 , H01L21/336
CPC分类号： H01L21/743 , H01L21/26513 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/49816 , H01L27/0694 , H01L27/10888 , H01L27/10894 , H01L29/66568 , H01L29/78 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548
摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
摘要翻译：描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部金属填充通孔的区域。

2. 发明申请

US20070099397A1 Microfeature dies with porous regions, and associated methods and systems 审中-公开
标题翻译：具有多孔区域的微特征，以及相关的方法和系统
公开(公告)号：US20070099397A1
公开(公告)日：2007-05-03
申请号：US11634417
申请日：2006-12-04
申请人： Kyle Kirby , Paul Morgan
发明人： Kyle Kirby , Paul Morgan
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/02126 , H01L21/02203 , H01L21/02321 , H01L21/02323 , H01L21/02337 , H01L21/02343 , H01L21/02351 , H01L21/31695 , H01L21/743 , H01L21/78
摘要： Microfeature dies with porous regions, and associated methods and systems are disclosed. A method in accordance with one embodiment of the invention includes forming a porous region between a die and a remainder portion of a microfeature workpiece, and separating the die from the remainder portion by removing at least a portion of the porous region. For example, the die can be removed from the remainder portion by making a cut at the porous region (e.g., with a rotating saw blade), etching material from the porous region, or directing a water jet at the porous region. In other embodiments, a porous region of the microfeature workpiece can receive conductive material to form a conductive pathway (e.g., a line and/or via) in the workpiece. In still further embodiments, the porous regions of the workpiece can be formed electrolytically with electrodes that are spaced apart from the workpiece and/or support relative movement between the electrodes and the workpiece.
摘要翻译：具有多孔区域的微特征模具以及相关方法和系统被公开。根据本发明的一个实施例的方法包括在模具和微特征工件的剩余部分之间形成多孔区域，并且通过去除多孔区域的至少一部分将模具与其余部分分离。例如，通过在多孔区域（例如，利用旋转的锯片）进行切割，从多孔区域蚀刻材料，或者在多孔区域引导水射流，可以将模具从剩余部分中除去。在其他实施例中，微特征工件的多孔区域可以接收导电材料以在工件中形成导电路径（例如，线路和/或通孔）。在另外的实施例中，可以用与工件间隔开的电极和/或支撑电极和工件之间的相对运动来电解形成工件的多孔区域。

3. 发明申请

US20070045858A1 Microfeature workpieces and methods for forming interconnects in microfeature workpieces 有权
标题翻译：微型工件和在微型工件中形成互连的方法
公开(公告)号：US20070045858A1
公开(公告)日：2007-03-01
申请号：US11218243
申请日：2005-09-01
申请人： Kyle Kirby , William Hiatt , Richard Stocks
发明人： Kyle Kirby , William Hiatt , Richard Stocks
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H01L21/76898 , H01L21/76868 , H01L21/76873 , H01L23/481 , H01L2924/0002 , H01L2924/00012 , H01L2924/00
摘要： Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. In one embodiment, a method of forming an interconnect in a microfeature workpiece includes forming a hole extending through a terminal and a dielectric layer to at least an intermediate depth in a substrate of a workpiece. The hole has a first lateral dimension in the dielectric layer and a second lateral dimension in the substrate proximate to an interface between the dielectric layer and the substrate. The second lateral dimension is greater than the first lateral dimension. The method further includes constructing an electrically conductive interconnect in at least a portion of the hole and in electrical contact with the terminal.
摘要翻译：在微型工件中形成互连的方法以及具有这种互连的微型工件在此公开。在一个实施例中，在微特征工件中形成互连的方法包括：将通过端子和电介质层延伸的孔形成在工件的衬底中的至少中间深度。该孔在电介质层中具有第一横向尺寸，并且该基板中的第二横向尺寸靠近介电层和基底之间的界面。第二横向尺寸大于第一横向尺寸。该方法还包括在孔的至少一部分中与端子电接触地构造导电互连。

4. 发明申请

US20070001168A1 Semiconductor components and assemblies including vias of varying lateral dimensions 有权
标题翻译：半导体元件和组件包括不同横向尺寸的通孔
公开(公告)号：US20070001168A1
公开(公告)日：2007-01-04
申请号：US11516424
申请日：2006-09-05
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/3114 , H01L23/3677 , H01L23/481 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2924/00011 , H01L2924/00014 , H05K1/115 , H05K2201/09563 , H05K2201/09845 , H05K2203/0733 , H01L2224/0401
摘要： Methods for forming vias are disclosed. The methods include providing a substrate having a first surface and an opposing, second surface. A first opening and a second opening are formed in a substrate such that the first opening and the second opening are in communication with each other. A portion of the first opening and the second opening are filled with a conductive material. Semiconductor devices, including the vias of the present invention, are also disclosed. A method of forming semiconductor components, semiconductor components and assemblies resulting therefrom, and an electronic system, including the vias of the present invention, are further disclosed.
摘要翻译：公开了形成通孔的方法。所述方法包括提供具有第一表面和相对的第二表面的基底。第一开口和第二开口形成在基板中，使得第一开口和第二开口彼此连通。第一开口和第二开口的一部分填充有导电材料。还公开了包括本发明的通孔的半导体器件。还公开了一种形成半导体部件，由其产生的半导体部件和组件以及包括本发明的通孔的电子系统的方法。

5. 发明申请

US20060261340A1 Microelectronic imagers and methods of packaging microelectronic imagers 有权
标题翻译：微电子成像器和包装微电子成像器的方法
公开(公告)号：US20060261340A1
公开(公告)日：2006-11-23
申请号：US11494453
申请日：2006-07-28
申请人： Warren Farnworth , Sidney Rigg , William Hiatt , Kyle Kirby , Peter Benson , James Wark , Alan Wood , David Hembree , Salman Akram , Charles Watkins
发明人： Warren Farnworth , Sidney Rigg , William Hiatt , Kyle Kirby , Peter Benson , James Wark , Alan Wood , David Hembree , Salman Akram , Charles Watkins
IPC分类号： H01L29/04 , H01L33/00 , H01L29/768 , H01L27/148 , H01L31/0203
CPC分类号： H01L27/14618 , H01L23/481 , H01L24/48 , H01L31/0203 , H01L31/02325 , H01L2224/48227 , H01L2924/00014 , H01L2924/01046 , H01L2924/01077 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/15174 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic imagers and methods for packaging microelectronic imagers are disclosed herein. In one embodiment, a microelectronic imaging unit can include a microelectronic die, an image sensor, an integrated circuit electrically coupled to the image sensor, and a bond-pad electrically coupled to the integrated circuit. An electrically conductive through-wafer interconnect extends through the die and is in contact with the bond-pad. The interconnect can include a passage extending completely through the substrate and the bond-pad with conductive fill material at least partially disposed in the passage. An electrically conductive support member is carried by and projects from the bond-pad. A cover over the image sensor is coupled to the support member.
摘要翻译：本文公开了微电子成像器和用于封装微电子成像器的方法。在一个实施例中，微电子成像单元可以包括微电子管芯，图像传感器，电耦合到图像传感器的集成电路以及电耦合到集成电路的接合焊盘。导电晶片互连延伸穿过管芯并且与焊盘接触。互连可以包括完全延伸穿过基底的通道和具有至少部分地设置在通道中的导电填充材料的接合垫。导电支撑构件由接合垫承载和突出。图像传感器上的盖连接到支撑构件。

6. 发明申请

US20060255826A1 Systems and methods for testing microelectronic imagers and microfeature devices 有权
标题翻译：用于测试微电子成像器和微特征器件的系统和方法
公开(公告)号：US20060255826A1
公开(公告)日：2006-11-16
申请号：US11409060
申请日：2006-04-24
申请人： Salman Akram , William Hiatt , Alan Wood , Charles Watkins , Kyle Kirby
发明人： Salman Akram , William Hiatt , Alan Wood , Charles Watkins , Kyle Kirby
IPC分类号： G01R31/26
CPC分类号： G01R31/2635 , G01R31/2831
摘要： Systems and methods for testing microelectronic imagers and microfeature devices are disclosed herein. In one embodiment, a method includes providing a microfeature workpiece including a substrate having a front side, a backside, and a plurality of microelectronic dies. The individual dies include an integrated circuit and a plurality of contact pads at the backside of the substrate operatively coupled to the integrated circuit. The method includes contacting individual contact pads with corresponding pins of a probe card. The method further includes testing the dies. In another embodiment, the individual dies can further comprise an image sensor at the front side of the substrate and operatively coupled to the integrated circuit. The image sensors are illuminated while the dies are tested.
摘要翻译：本文公开了用于测试微电子成像器和微特征器件的系统和方法。在一个实施例中，一种方法包括提供微功能工件，其包括具有正面，背面和多个微电子管芯的衬底。各个管芯包括集成电路和在衬底的背面可操作地耦合到集成电路的多个接触焊盘。该方法包括使各个接触垫与探针卡的相应引脚接触。该方法还包括测试模具。在另一个实施例中，各个管芯还可以包括在衬底的前侧的图像传感器，并可操作地耦合到集成电路。在测试模具时，图像传感器被照亮。

7. 发明申请

US20060192230A1 Image sensor packages and frame structure thereof 有权
标题翻译：图像传感器封装及其框架结构
公开(公告)号：US20060192230A1
公开(公告)日：2006-08-31
申请号：US11411265
申请日：2006-04-26
申请人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
发明人： Alan Wood , Kyle Kirby , Warren Farnworth , Salman Akram
IPC分类号： H01L27/148 , H01L31/0203
CPC分类号： H01L27/14618 , B33Y80/00 , H01L27/14625 , H01L2224/48091 , H01L2924/00014
摘要： A semiconductor package such as an image sensor package. A frame structure includes an array of frames, each having an aperture therethrough, into which an image sensor die in combination with a cover glass, filter, lens or other components may be installed in precise mutual alignment. Singulated image sensor dice and other components may be picked and placed into each frame of the frame structure. Alternatively, the frame structure may be configured to be aligned with and joined to a wafer bearing a plurality of image sensor dice, wherein optional, downwardly protruding skirts along peripheries of the frames may be received into kerfs cut along streets between die locations on the wafer, followed by installation of other package components. In either instance, the frame structure in combination with singulated image sensor dice or a joined wafer is singulated into individual image sensor packages. Various external connection approaches may be used.
摘要翻译：诸如图像传感器封装的半导体封装。框架结构包括每个具有穿过其中的孔的框架阵列，图像传感器与盖玻片，过滤器，透镜或其它部件组合的模具可以精确相互对准地安装在该框架中。单片图像传感器骰子和其他组件可以被拾取并放置在框架结构的每个帧中。或者，框架结构可以被配置为与承载多个图像传感器骰子的晶片对准并且连接到其上，其中沿着框架的周边的任选的向下突出的裙边可以被接收到沿着晶片上的模具位置之间沿着街道切割的切口，然后安装其他包装组件。在任一情况下，将帧结构与单独的图像传感器芯片或连接的晶片组合成单独的图像传感器封装。可以使用各种外部连接方法。

8. 发明申请

US20060181295A1 Method for fabricating an interconnect for semiconductor components 失效
标题翻译：制造半导体元件的互连的方法
公开(公告)号：US20060181295A1
公开(公告)日：2006-08-17
申请号：US11396790
申请日：2006-04-03
申请人： Kyle Kirby
发明人： Kyle Kirby
IPC分类号： G01R31/02
CPC分类号： G01R1/06711 , G01R1/0483 , G01R1/07314 , Y10T29/49117 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151
摘要： A method for fabricating an interconnect for testing a semiconductor component includes the steps of providing a substrate, and forming interconnect contacts on the substrate configured to electrically engage component contacts on the component. The interconnect contacts include flexible spring segments defined by grooves in the substrate, shaped openings in the substrate, or shaped portions of the substrate. The spring segments are configured to flex to exert spring forces on the component contacts, and to compensate for variations in the size or planarity of the component contacts. The interconnect can be configured to test wafer sized components, or to test die sized components.
摘要翻译：一种用于制造用于测试半导体部件的互连件的方法包括以下步骤：提供衬底，以及在所述衬底上形成配置成电接合所述部件上的部件触点的互连触点。互连触点包括由衬底中的凹槽限定的柔性弹簧段，衬底中的成形开口或衬底的成形部分。弹簧段构造成弯曲以在部件触点上施加弹簧力，并且补偿部件触头的尺寸或平面度的变化。互连可以配置为测试晶片尺寸的组件，或者测试模具尺寸的组件。

9. 发明申请

US20060180941A1 Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements 有权
标题翻译：衬底，半导体管芯，多芯片模块和包括包括多个导电元件的通孔结构的系统
公开(公告)号：US20060180941A1
公开(公告)日：2006-08-17
申请号：US11405045
申请日：2006-04-17
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： H01L23/48
CPC分类号： B82Y10/00 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2221/1094 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/0557 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2224/05599 , H01L2224/05099
摘要： A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric material, a plurality of smaller, through holes may be formed in the dielectric material, and conductive material may be deposited in the smaller holes. Another method includes forming laterally separated protruding structures in a cavity of a substrate, depositing conductive material over the structures and dielectric material between the structures, and thinning the substrate. Alternatively, conductive nanotubes may be formed in the cavity, and dielectric material may be deposited that surrounds the nanotubes. A method of forming a multichip module includes forming at least one via extending through a plurality of stacked dice that includes a plurality of conductive elements.
摘要翻译：形成多导体通孔的方法包括在衬底的至少一个通孔中形成至少一个种子层，选择性地图案化种子层以形成多个横向分离的区域，并在该区域上沉积金属。或者，通孔可以基本上填充有介电材料，可以在电介质材料中形成多个更小的通孔，并且导电材料可以沉积在较小的孔中。另一种方法包括在衬底的空腔中形成横向分离的突出结构，在结构之间沉积导电材料并在该结构之间沉积电介质材料，并使衬底变薄。或者，可以在空腔中形成导电纳米管，并且可以沉积围绕纳米管的电介质材料。一种形成多芯片模块的方法包括形成至少一个通过包括多个导电元件的多个堆叠的骰子延伸的通孔。

10. 发明申请

US20060145353A1 Semiconductor interconnect having dome shaped conductive spring contacts 审中-公开
标题翻译：半导体互连具有圆顶形导电弹簧触点
公开(公告)号：US20060145353A1
公开(公告)日：2006-07-06
申请号：US11366073
申请日：2006-03-02
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： H01L23/48
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

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